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XA-SCC CMOS 16-bit communications microcontroller
Preliminary specification Supersedes data of 1999 Feb 23 IC25 Data Handbook 1999 Mar 29
Philips Semiconductors
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
GENERAL DESCRIPTION
The XA-SCC device is a member of Philips' XA (eXtended Architecture) family of high performance 16-bit single-chip microcontrollers. The XA-SCC includes a complete onboard DRAM controller capable of supporting up to 32MegaBytes of DRAM. The XA-SCC device combines many powerful communications oriented peripherals on one chip. 4 Full Function SCC's, 8 DMA channels (2 per SCC), hardware autobaud up to 921.6Kbps, IDL TDM interface, two timers/counters, 1 watchdog timer, and multiple general purpose I/O ports. It is suited for many high performance embedded communications functions, including ISDN terminal adaptors and Asynchronous Muxes.
* Memory controller also generates 6 chip selects to support
SRAM, ROM, Flash, EPROM, peripheral chips, etc. without external glue.
* Supports off-chip addressing up to 32 MB (2 x 2**24 address
spaces) in Harvard architecture, or 16MB in unified memory configuration.
* A clock output reference "ClkOut" is added to simplify external bus
interfacing.
* High performance 8-channel DMA Controller offloads the CPU for
moving data to/from SCC's and memory.
* Two standard counter/timers with enhanced features (same as
XA-G3 T0, T1). Both timers have a toggle output capability.
SPECIFIC FEATURES OF THE XA-SCC
range, available in 100 pin LQFP package.
* 3.3V to 5.5V operation to 30MHz over the industrial temperature * 4 onboard SCC's for 2B+D plus Asynch port, or any combination
of 4 sync/async ports. Industry standard IDL and SCP interfaces for glueless connection to U-Chip or S/T chip. Sync data rates to 4Mbps. Asynch data rates to 921.6Kbps with/without autobaud.
* Watchdog timer. * Seven standard software interrupts, plus four High Priority
Software Interrupts, plus 7 levels of Hardware Event Interrupts.
* Active low reset output pin indicates all internal reset occurrences
(watchdog reset and the RESET instruction). A reset source register allows program determination of the cause of the most recent reset.
* Complete onboard DRAM controller supports 5 banks of up to
8MBytes each. Interfaces without glue chips to most industry standard DRAMs.
* 32 General Purpose I/O pins, each with 4 programmable output
configurations.
* Power saving operating modes: Idle and Power-Down. Wake-Up
from power-down via an external interrupt is supported.
ORDERING INFORMATION
ROMless Only PXASCCKFBE TEMPERATURE RANGE C AND PACKAGE -40 to +85, 100-pin Low Profile Quad Flat Pkg. (LQFP) FREQ (MHz) 30 PACKAGE DRAWING NUMBER SOT407-1
NOTE: 1. K=30MHz, F = (-40 to +85 C), BE = LQFP
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
PIN CONFIGURATION
P3.3_Timer1_BRG1_Sync1 56 P3.0_CS4_RAS4_RTClk1
P1.7_BRG2_Sync2
67 P3.7_Int1_TRClk1
P3.1_CS5_RAS5_RTS1
P3.2_Timer0_ResetOut
71 P1.3_TRClk2
70 P1.2_RTClk2
XTALOUT
Reset_In
XTALIN
VDD
VSS
BHE_CASH
P1.5_CTS2
P3.4_CTS1
P1.6_RTS2
P1.0_RxD2
P3.5_RxD1
BLE_CASL
P1.1_TxD2
P3.6_TxD1
P1.4_CD2
WAIT_Size16 52
75
74
73
72
69
68
66
65
64
63
62
61
60
59
58
57
55
54
53
VSS VDD CD1_Int2 Int0 P2.0_RxD3 P2.1_TxD3 P2.2_RTClk3 P2.3_ComClk_TRClk3 P2.4_CD3 P2.5_CTS3 P2.6_RTS3 P2.7_Sync3_BRG3 VSS VDD P0.0_Sync0_BRG0_SDS2 P0.1_RTS0_L1RQ P0.2_CTS0_L1GR P0.3_CD0_L1SY1 P0.4_TRClk0_SDS1 P0.5_RTClk0_L1Clk TxD0_L1TxD RxD0_L1RxD SCPClk P0.6_SCPTx
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 PIN INDEX MOLD MARK MOLD MARK
51 50 49 48 47 46 45 44 43 42 41 40
OE
WE CS0 CS1_RAS1 CS2_RAS2 CS3_RAS3 ClkOut VSS VDD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 VDD VSS D2 D1
XA-SCC PLASTIC LOW PROFILE QUAD FLAT PACKAGE (LQFP) Top View
39 38 37 36 35 34 33 32 31 30 29 28 27 26
P0.7_SCPRx 100 10 12 13 14 15 16 17 18 19 20 21 22 23 24 A19 25 D0 11 A8 (A19_A20) 1 2 3 4 5 6 7 8 9
A7 (A21_A22)
A15 (A6_A22)
A11 (A2)
A16 (A7_A20_A21)
A17 (A8_A18_A19)
A9 (A0_A18)
A10 (A1)
A12 (A3)
A13 (A4)
A14 (A5)
A0
A1
A2
A3
A4
A5
A6
VSS
VDD
VSS
NOTE: Address lines output during various DRAM CAS cycles are shown in parentheses. See DRAM controller for details.
SU01120
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VDD
A18
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
LOGIC SYMBOL
VDD Int0 XTAL1 MISC. Int2 CS4, RAS4 CS5, RAS5 ResetOut, Timer0 Timer1 BRG1, Sync1 CTS1 RxD1 TxD1 Int1 TRClk1 SCC1 CD1 RTClk1 RTS1 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 CS1, RAS1 CS0 CS3, RAS3 CS2, RAS2 XTAL2 PORT3 VSS
SCC3 RxD3 TxD3 RTClk3 ComClk, TRClk3 CD3 CTS3 RTS3 BRG3, Sync3
PORT2 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 D15 - D0 A19 - A0 ( DRAM A22 - A0)
SCC2
PORT1
RxD2 TxD2 RTClk2 TRClk2 CD2 CTS2 RTS2 BRG2, Sync2
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 OE WE ClkOut CASH, BHE CASL, BLE
IDL L1TxD L1RxD SDS2 L1RQ L1GR L1SY1 SDS1 L1Clk
SCC0 TxD0 RxD0 BRG0, Sync0 RTS0 CTS0 CD0 TRClk0 RTClk0
PORT0 Wait, Size16 ResetIn
0.0 0.1 0.2 0.3 0.4 0.5
SCPTx SCPRx SCPClk
0.6 0.7
SU01121
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
BLOCK DIAGRAM
XA CPU
INTERRUPT CONTROLLER
256 BYTES RAM
RESET CONTROL & STATUS
TIMERS 0,1 WATCHDOG TIMER
SCP INTERFACE PORTS and PIN FUNCTION MUX IDL INTERFACE MIF and DRAM CONTROLLER DMA CHANNELS x8 SCCs x4
SCP PORT
AUTOBAUD x4
GPIO
EXTERNAL MEMORY and I/O BUS
IDL and NMSI PORTS
v.54 2047 x2
NOTE: Main Communications Data paths shown in bold.
SU01122
Figure 1. XA-SCC Block Diagram
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
PIN DESCRIPTIONS
MNEMONIC VSS LQFP PIN NO. 1, 19, 28, 44, 59, 76, 88 2, 20, 29, 43, 62, 77, 89 55 52 60 61 49 TYPE I Ground: 0V reference. NAME AND FUNCTION
VDD
I
Power Supply: This is the power supply voltage for normal, idle, and power down operation.
ResetIn WAIT/Size16 XTALIn XTALOut CS0
I I I I O
Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor to begin execution at the address contained in the reset vector. Wait/Size16: During Reset, this input determines bus size for boot device (1 = 16 bit boot device, 0 = 8 bit.) During normal operation this is the Wait input (1 = Wait, 0 = Proceed.) Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal clock generator circuits. Crystal 2: Output from the oscillator amplifier. Chip Select 0: This output provides the active low chip select to the boot device (usually ROM or Flash.) It cannot be connected to DRAM. From reset, it is enabled and mapped to an address range based at 000000h. It can be remapped to a higher base in the address map (see the Memory Interface chapter in the XA-SCC User Manual.) Chip Select 1 , RAS 1: Chip selects 1 through 5 come out of reset disabled. They can be programmed to function as normal chip selects, or as RAS strobes to DRAM. CS1 can be "swapped" with CS0 (see the SWAP operation and control bit in the Memory Controller chapter of the XA-SCC User Manual.) CS1 is usually mapped to be based at 000000h eventually, but is capable of being based anywhere in the 16MB space. CS2 , RAS 2: Active low chip selects CS1 through CS5 come out of reset disabled. They can be programmed to function as normal chip selects, or as RAS strobes to DRAM. CS2 through CS5 are not used with the "SWAP" operation (see Memory Controller chapter in the XA-SCC User Manual.) They are mappable to any region of the 16MB address space. CS3, RAS 3: See chip select 2 for description.
CS1_RAS1
48
O
CS2_RAS2
47
O
CS3_RAS3
46
O
see pins 56,57 for 2 more chip selects WE OE BLE_CASL BHE_CASH ClkOut 50 51 54 53 45 O O O O O Write Enable: Goes active low during all bus write cycles only. Output Enable: Goes active low during all bus read cycles only. Byte Low Enable or CAS_Low_Byte: Goes active low during all bus cycles that access D7-D0, read or write, Generic or DRAM. Functions as CAS during DRAM cycles. Byte High Enable or CAS_High_Byte: Goes active low during all bus cycles that access D15-D8, read or write, Generic or DRAM. Functions as CAS during DRAM cycles. Clock Output: This pin outputs a buffered version of the internal CPU clock. The clock output may be used in conjunction with the external bus to synchronize WAIT state generators, etc. The clock output may be disabled by software. WARNING: The capacitive loading on this output must not exceed 40pF. Address[19:0]: These address lines output a19-a0 during generic (SRAM etc) bus cycles. DRAMs are connected only to pins 22,21, 18-10 (pins A17 to A7; see User Manual MIF Chapter for connecting various DRAM sizes); the appropriate address values are multiplexed onto these 11 pins for RAS and CAS during DRAM bus cycles. Data[15:0]: Bi-directional data bus, D15-D0. P0.0_Sync0_BRG0_SDS2: Port 0 Bit 0, or SCC0 Sync input or output, or SCC0 BRG output, or SCC0 TxClk output, or IDL SDS2 output. P0.1_RTS0_L1RQ: Port0 Bit1 , or SCC0 RTS (Request to send) output, or IDL L1RQ (D Channel Request) output. P0.2_CTS0_L1GR: Port 0 Bit2, or SCC0 CTS (Clear to Send) input or IDL L1GR (D Channel Grant) input P0.3_CD0_L1SY1: Port 0 Bit 3, or SCC0 Carrier Detect input, or IDL Sync input. P0.4_TRClk0_SDS1: Port 0 Bit 4, or SCC0 TR clock input, or IDL SDS1 output.
A19-A0
24-21, 18-3
O
D15-D0 P0.01 P0.11 P0.21 P0.31 P0.41, 2
42-30, 27-25 90 91 92 93 94
I/O I/O I/O I/O I/O I/O
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
MNEMONIC P0.51, 2 P0.61 P0.71 TxD0_L1TxD RxD0_L1RxD SCPClk P1.0 P1.1 P1.22 P1.32 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.22 P2.32 P2.4 P2.5 P2.6 P2.7 P3.02 P3.1 P3.2
LQFP PIN NO. 95 99 100 96 97 98 68 69 70 71 72 73 74 75 80 81 82 83 84 85 86 87 56 57 58
TYPE I/O I/O I/O O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
NAME AND FUNCTION P0.5_RTClk0_L1Clk: Port 0 Bit 5, or SCC0 RT clock input, or IDL Clock input. P0.6_SCPTx: Port 0 Bit 6, or SCP interface Transmit data output. P0.7_SCPRx: Port 0 Bit 7, or SCP interface Receive data input. TxD0_L1Txd: Transmit data for SCC0 in NMSI mode, or for IDL bus RxD0_L1Rxd: Receive data for SCC0 in NMSI mode, or for IDL bus SCPClk: This output provides the gated clock for the SCP bus. P1.0_RxD2: Port 1 Bit 0, or SCC2 RxD input P1.1_TxD2: Port 1 Bit 1, or SCC2 TxD output P1.2_RTClk2: Port 1 Bit 2, or SCC2 RT Clock input P1.3_TRClk2: Port 1 Bit 3, or SCC2 TR Clock input P1.4_CD2: Port 1 Bit 4, or SCC2 Carrier Detect input P1.5_CTS2: Port 1 Bit 5, or SCC2 Clear To Send input P1.6_RTS2: Port 1 Bit 6, or SCC2 Request To Send output P1.7_BRG2_Sync2: Port 1 Bit 7, or SCC2 Sync input or output, or BRG output, or TxClk output (see SCC clocks diagrams in User Manual Chp 5) P2.0_RxD3: Port 2 Bit 0, or SCC3 Rx Data input P2.1_TxD3: Port 2 Bit 1, or SCC3 Tx Data output P2.2_RTClk3: Port 2 Bit 2, or SCC3 RT Clock input P2.3_ComClk_TRClk3: Port 2 Bit 3, or SCC3 TR Clock input P2.4_CD3: Port 2 Bit 4, or SCC3 Carrier Detect input P2.5_CTS3: Port 2 Bit 5, or SCC3 Clear To Send input P2.6_RTS3: Port 2 Bit 6, or SCC3 Request To Send output P2.7_Sync3_BRG3: Port 2 Bit 7, or SCC3 Sync input or output, or BRG output, or TxClk output (see SCC clocks diagrams in User Manual Chp 5) P3.0_CS4_RAS4_RTClk1: Port 3 Bit 0, or CS4 or RAS4 output, or SCC1 RT Clock input P3.1_CS5_RAS5_RTS1: Port 3 Bit 1, or CS5 or RAS5 output, or SCC1 Request To Send output P3.2_Timer0_ResetOut: Port 3 Bit 2, or Timer0 input or output, or ResetOut output. ResetOut: If the ResetOut function is selected, this pin outputs a low whenever the XA-SCC processor is reset by an internal source (watchdog reset or the RESET instruction.) WARNING: Unlike the other 31 GPIO pins, during power up reset, this pin can output a strongly driven low pulse. The duration of this low pulse ranges from 0ns to 258 system clocks, starting at the time that VCC is valid. The state of the ResetIn pin does not affect this pulse. When used as GPIO, this pin can also be driven low by software without resetting the XA-SCC.
P3.3 P3.4 P3.5 P3.6 P3.72 CD1_Int2
63 64 65 66 67 78 79
I/O I/O I/O I/O I/O I I
P3.3_Timer1_BRG1_Sync1: Port 3 Bit 3, or Timer1 input or output, or SCC1 BRG output, or SCC1 Sync input or output P3.4_CTS1: Port 3 Bit 4, or SCC1 Clear To Send input P3.5_RxD1: Port 3 Bit 5, or SCC1 Receive Data input P3.6_TxD1: Port 3 Bit 6, or SCC1 Transmit Data output P3.7_Int1_TRClk1: Port 3 Bit 7, or External Interrupt1 input, or SCC1 TR Clock input CD1_Int2: SCC1 Carrier Detect, or External Interrupt 2 External Interrupt 0
Int0
NOTES: 1. See XA-SCC User Guide "Pins Chapter" for how to program selection of pin functions. 2. RTClk input is usually used for Rx Clock if an external clock is needed, but can be used for either Rx or Tx or both. TRClk is usually used for Tx Clock, but can be used for Rx or Tx or both.
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
CONTROL REGISTER OVERVIEW
There are two types of control registers in the XA-SCC, these are SFRs (Special Function Registers), and MMRs (Memory Mapped Registers.) The SFR registers, with the exception of MRBL, MRBH, MICFG, BCR, BRTH, BRTL, and RSTSRC are the standard XA core registers. See WARNINGs about BCR, BRTH, and BRTL in the Table below.
SFRs are accessed by "direct addressing" only (see IC25 XA User Manual for direct addressing.) The MMRs are specific to the XA-SCC on board peripherals, and can be accessed by any addressing mode that can be used for off chip data accesses. The MMRs are implemented in a relocatable block. See the MIF chapter in the XA-SCC User Manual for details on how to relocate the MMRs by writing a new base address into the MRBL and MRBH (MMR Base Low and High) registers.
Table 1. Special Function Registers (SFR)1, 2, 3
NAME BCR BTRH BTRL DESCRIPTION Bus Configuration Reg RESERVED--see warning Bus Timing Reg High Bus Timing Reg Low SFR Address 46Ah 469h 468h BIT FUNCTIONS AND ADDRESSES MSB LSB RESET VALUE 07h FFh EFh
WARNING--Never write to the BCR register in the XA-SCC part--it is initialized to 07h, the only legal value. This is not the same as for other XA derivatives. WARNING--Immediately after reset, always write BTRH = 51h, followed by writing order. NOPS. BTRL = 40h in that order Follow these two writes with five NOPS This is not the same as for other XA derivatives.
MRBL# MRBH# MICFG#
MMR Base Address Low MMR Base Address High ClkOut Tri-St Enable 1 = Enabled
496h 497h 499h
MA15 MA23 -
MA14 MA22 -
MA13 MA21 -
MA12 MA20 -
- MA19 -
- MA18 -
- MA17 -
MRBE MA16 CLKOE
x0h xx 01h
CS DS ES
Code Segment Data Segment Extra Segment
443h 441h 442h
00h 00h 00h
33F IEH* Interrupt Enable High 427h EHSWR3
33E EHSWR2
33D EHSWR1
33C EHSWR0
33B ESCP
33A EAuto
339 ESC23
338 ESC01 00h
337 IEL* IPA0 IPA1 IPA2 IPA3 IPA4 IPA5 IPA6 IPA7 Interrupt Enable Low Interrupt Priority A0 Interrupt Priority A1 Interrupt Priority A2 Interrupt Priority A3 Interrupt Priority A4 Interrupt Priority A5 Interrupt Priority A6 Interrupt Priority A7 426h 4A0h 4A1h 4A2h 4A3h 4A4h 4A5h 4A6h 4A7h - - - - EA - - -
336 EDMAH
335 EDMAL PT0 PT1 PDMAL
334 EX2
333 ET1 - - - - - - - -
332 EX1
331 ET0 PX0 PX1 PX2 PDMAH PSC01 PAutoB PHSWR0 PHSWR2
330 EX0 00h 00h 00h 00h 00h 00h 00h 00h 00h
Reserved PSC23 PSCP PHSWR1 PHSWR3
387 P0* Port 0 430h 38F P1* Port 1 431h 397 P2* Port 2 432h
386
385
384
383
382
381
380 FFh
38E
38D
38C
38B
38A
389
388 FFh
396
395
394
393
392
391
390 FFh
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
NAME
DESCRIPTION
SFR Address
BIT FUNCTIONS AND ADDRESSES MSB 39F 39E 39D 39C 39B 39A 399 LSB 398
RESET VALUE
P3*
Port 3
433h
FFh
P0CFGA P1CFGA P2CFGA P3CFGA P0CFGB P1CFGB P2CFGB P3CFGB
Port 0 Configuration A Port 1 Configuration A Port 2 Configuration A Port 3 Configuration A Port 0 Configuration B Port 1 Configuration B Port 2 Configuration B Port 3 Configuration B
470h 471h 472h 473h 4F0h 4F1h 4F2h 4F3h
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4
227 PCON* Power Control Reg 404h -
226 -
225 -
224 -
223 -
222 -
221 PD
220 IDL 00h
20F PSWH* Program Status Word High 401h SM 207 PSWL* Program Status Word Low 400h C 217 PSW51* 80C51 compatible PSW 402h C
20E TM 206 AC 216 AC
20D RS1 205 - 215 F0
20C RS0 204 - 214 RS1
20B IM3 203 - 213 RS0
20A IM2 202 V 212 V
209 IM1 201 N 211 F1
208 IM0 200 Z 210 P Note 6 Note 5 Note 5
RSTSRC
Reset Source Reg
463h
ROEN
-
-
-
-
R_WD
R_CMD
R_EXT
Note 7
RTH0 RTH1 RTL0 RTL1
Timer 0 Reload High Timer 1 Reload High Timer 0 Reload Low Timer 1 Reload Low
455h 457h 454h 456h
00h 00h 00h 00h
SCR
System Configuration Reg
440h
-
-
-
-
PT1
PT0
CM
PZ
00h
21F SSEL* Segment Selection Reg 403h ESWEN
21E R6SEG
21D R5SEG
21C R4SEG
21B R3SEG
21A R2SEG
219 R1SEG
218 R0SEG 00h
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
NAME SWE
DESCRIPTION Software Interrupt Enable
SFR Address 47Ah -
BIT FUNCTIONS AND ADDRESSES MSB SWE7 SWE6 SWE5 SWE4 SWE3 SWE2 LSB SWE1
RESET VALUE 00h
357 SWR* Software Interrupt Request 42Ah -
356 SWR7
355 SWR6
354 SWR5
353 SWR4
352 SWR3
351 SWR2
350 SWR1 00h
287 TCON* TH0 TH1 TL0 TL1 TMOD Timer 0/1 Control Timer 0 High Timer 1 High Timer 0 Low Timer 1 Low Timer 0/1 Mode 410h 451h 453h 450h 452h 45Ch GATE TF1
286 TR1
285 TF0
284 TR0
283 IE1
282 IT1
281 IE0
280 IT0 00h 00h 00h 00h 00h
C/T
M1
M0
GATE
C/T
M1
M0
00h
28F TSTAT* Timer 0/1 Extended Status 411h -
28E -
28D -
28C -
28B -
28A T1OE
289 -
288 T0OE 00h
2FF WDCON* WDL WFEED1 WFEED2 Watchdog Control Watchdog Timer Reload Watchdog Feed 1 Watchdog Feed 2 41Fh 45Fh 45Dh 45Eh PRE2
2FE PRE1
2FD PRE0
2FC -
2FB -
2FA WDRUN
2F9 WDTOF
2F8 - Note 8 00h xx xx
NOTES: * SFRs marked with an asterisk (*) are bit addressable. # SFRs marked with a pound sign (#) are additional SFR registers specific to the XA-SCC. 1. The XA-SCC implements an 8-bit SFR bus, as stated in Chapter 8 of the IC25 Data Handbook XA User Guide. All SFR accesses must be 8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data in the upper byte. 2. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other purposes in future XA derivatives. The reset value shown for these bits is 0. 3. The XA guards writes to certain bits (typically interrupt flags) that may be written by a peripheral function. This prevents loss of an interrupt or other status if a bit was written directly by a peripheral action between the read and write of an instruction that performs a read-modify-write operation. XA-SCC SFR bits that are guarded in this manner are: TF1, TF0, IE1, and IE0 (in TCON), and WDTOF (in WDCON). 4. Port configurations default to quasi-bidirectional when the XA begins execution after reset. Thus all PnCFGA registers will contain FFh and PnCFGB register will contain 00h. See warning in XA-SCC User Manual about P3.2_Timer0_ResetOut pin during first 258 clocks after power up. Basically, during this period, this pin may output a strongly driven low pulse. If the pulse does occur, it will terminate in a transition to high at a time no later than the 259th system clock after valid VCC power up. 5. SFR is loaded from the reset vector. 6. F1, F0, and P reset to 0. All other bits are loaded from the reset vector. 7. The RSTSRC register reflects the cause of the last XA reset. One bit will be set to 1, the others will be 0. RSTSRC[7] enables the ResetOut function; 1 = Enabled, 0 = Disabled. See XA-SCC User Manual for details; RSTSRC[7] differs in function from most other XA derivatives. 8. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes.
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Table 2. Memory Mapped Registers
MMR Name Read/Write or Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO Size Address Offset 800h 802h 804h 806h 808h 80Ah 80Ch 80Eh 810h 812h 814h 816h 818h 81Ah 81Ch 81Eh 828h 82Ah 820h 822h 824h 8 8 8 8 8 826h 828-82Ah 82Ch 82Eh 830h 832h 834h 836-83Eh SCC1 Registers SCC1 Write Register 0 SCC1 Write Register 1 SCC1 Write Register 2 SCC1 Write Register 3 SCC1 Write Register 4 SCC1 Write Register 5 SCC1 Write Register 6 SCC1 Write Register 7 SCC1 Write Register 8 SCC1 Write Register 9 SCC1 Write Register 10 SCC1 Write Register 11 SCC1 Write Register 12 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 840h 842h 844h 846h 848h 84Ah 84Ch 84Eh 850h 852h 854h 856h 858h Command register Tx/Rx Interrupt & data transfer mode Extended Features Control Receive Parameter and Control Tx/Rx misc. parameters & mode Tx. parameter and control Sync character or SDLC address field or Match Character 0 Sync character or SDLC flag or Match Character 1 Transmit Data Buffer Master Interrupt control Misc. Tx/Rx control register Clock Mode Control Lower Byte of Baud rate time constant 00h xx xx 00h 00h 00h 00h xx xx xx 00h xx 00h Loop/clock status Interrupt Pending Bits see WR16 and WR17 above SDLC byte count low register SDLC byte count high & FIFO status Receive Buffer Command register Tx/Rx Interrupt & data transfer mode Extended Features Control Receive Parameter and Control Tx/Rx misc. parameters & mode Tx. parameter and control Sync character or SDLC address field or Match Character 0 Sync character or SDLC flag or Match Character 1 Transmit Data Buffer Master Interrupt control Misc. Tx/Rx control register Clock Mode Control Lower Byte of Baud rate time constant Upper Byte of Baud rate time constant Misc. Control bits External/Status interrupt control Match Character 2 (WR16) Match Character 3 (WR17) Tx/Rx buffer and external status Receive condition status/residue code Description Reset Value 00h xx xx 00h 00h 00h 00h xx xx xx 00h xx 00h 00h xx f8h 00h 00h -- -- -- -- -- -- -- -- -- -- --
SCCO Registers SCC0 Write Register 0 SCC0 Write Register 1 SCC0 Write Register 2 SCC0 Write Register 3 SCC0 Write Register 4 SCC0 Write Register 5 SCC0 Write Register 6 SCC0 Write Register 7 SCC0 Write Register 8 SCC0 Write Register 9 SCC0 Write Register 10 SCC0 Write Register 11 SCC0 Write Register 12 SCC0 Write Register 13 SCC0 Write Register 14 SCC0 Write Register 15 SCC0 Write Register 16 SCC0 Write Register 17 SCC0 Read Register 0 SCC0 Read Register 1 Reserved--do not write SCC0 Read Register 3 see WR16 and 17 SCC0 Read Register 6 SCC0 Read Register 7 SCC0 Read Register 8 Reserved SCC0 Read Register 10 Reserved 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
1999 Mar 29
11
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
MMR Name SCC1 Write Register 13 SCC1 Write Register 14 SCC1 Write Register 15 SCC1 Write Register 16 SCC1 Write Register 17 SCC1 Read Register 0 SCC1 Read Register 1 Reserved SCC1 Read Register 3 see WR16 and 17 SCC1 Read Register 6 SCC1 Read Register 7 SCC1 Read Register 8 Reserved SCC1 Read Register 10 Reserved SCC2 Write Register 0 SCC2 Write Register 1 SCC2 Write Register 2 SCC2 Write Register 3 SCC2 Write Register 4 SCC2 Write Register 5 SCC2 Write Register 6 SCC2 Write Register 7 SCC2 Write Register 8 SCC2 Write Register 9 SCC2 Write Register 10 SCC2 Write Register 11 SCC2 Write Register 12 SCC2 Write Register 13 SCC2 Write Register 14 SCC2 Write Register 15 SCC2 Write Register 16 SCC2 Write Register 17 SCC2 Read Register 0 SCC2 Read Register 1 Reserved SCC2 Read Register 3 see WR16 and 17 SCC2 Read Register 6 SCC2 Read Register 7 SCC2 Read Register 8 Reserved SCC2 Read Register 10 Reserved
Read/Write or Read Only R/W R/W R/W R/W R/W RO RO RO RO RO RO RO
Size 8 8 8 8 8 8 8 8 8 8 8 8
Address Offset 85Ah 85Ch 85Eh 868h 86Ah 860h 862h 864h 866h 868-86Ah 86Ch 86Eh 870h 872h 874h 876-87Eh Loop/clock status Misc. Control bits
Description Upper Byte of Baud rate time constant External/Status interrupt control Match Character 2 (WR16) Match Character 3 (WR17) Tx/Rx buffer and external status Receive condition status/residue code Interrupt Pending Bits see WR16 and WR17 above SDLC byte count low register SDLC byte count high & FIFO status Receive Buffer
Reset Value 00h xx f8h 00h 00h -- -- -- -- -- -- -- -- -- -- --
SCC2 Registers R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 880h 882h 884h 886h 888h 88Ah 88Ch 88Eh 890h 892h 894h 896h 898h 89Ah 89Ch 89Eh 8A8h 8AAh 8A0h 8A2h 8A4h 8A6h 8A8-8AAh 8ACh 8AEh 8B0h 8B2h 8B4h 8B6-8BEh Loop/clock status Interrupt Pending Bits see WR16 and WR17 above SDLC byte count low register SDLC byte count high & FIFO status Receive Buffer Command register Tx/Rx Interrupt & data transfer mode Extended Features Control Receive Parameter and Control Tx/Rx misc. parameters & mode Tx. parameter and control Sync character or SDLC address field or Match Character 0 Sync character or SDLC flag or Match Character 1 Transmit Data Buffer Master Interrupt control Misc. Tx/Rx control register Clock Mode Control Lower Byte of Baud rate time constant Upper Byte of Baud rate time constant Misc. Control bits External/Status interrupt control Match Character 2 (wr16) Match Character 3 (wr17) Tx/Rx buffer and external status Receive condition status/residue code 00h xx xx 00h 00h 00h 00h xx xx xx 00h xx 00h 00h xx f8h 00h 00h -- -- -- -- -- -- -- -- -- -- --
1999 Mar 29
12
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
MMR Name
Read/Write or Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO
Size
Address Offset 8C0h 8C2h 8C4h 8C6h 8C8h 8CAh 8CCh 8CEh 8D0h 8D2h 8D4h 8D6h 8D8h 8DAh 8DCh 8DEh 8E8h 8EAh 8E0h 8E2h 8E4h 8E6h 8ECh 8EEh 8F0h 8F2h 8F4h 8F6-8FEh Command register
Description
Reset Value 00h xx xx 00h 00h 00h 00h xx xx xx 00h xx 00h 00h xx f8h 00h 00h -- -- -- -- -- -- -- -- -- --
SCC3 Registers SCC3 Write Register 0 SCC3 Write Register 1 SCC3 Write Register 2 SCC3 Write Register 3 SCC3 Write Register 4 SCC3 Write Register 5 SCC3 Write Register 6 SCC3 Write Register 7 SCC3 Write Register 8 SCC3 Write Register 9 SCC3 Write Register 10 SCC3 Write Register 11 SCC3 Write Register 12 SCC3 Write Register 13 SCC3 Write Register 14 SCC3 Write Register 15 SCC3 Write Register 16 SCC3 Write Register 17 SCC3 Read Register 0 SCC3 Read Register 1 Reserved SCC3 Read Register 3 SCC3 Read Register 6 SCC3 Read Register 7 SCC3 Read Register 8 Reserved SCC3 Read Register 10 Reserved DMA Control Register Ch.0 Rx FIFO Control & Status Reg Ch.0 Rx Segment Register Ch.0 Rx Buffer Base Register Ch.0 Rx Buffer Bound Register Ch.0 Rx Address Pointer Reg Ch.0 Rx Byte Count Register Ch.0 Rx Data FIFO Register Ch.0 Lo Rx Data FIFO Register Ch.0 Hi Rx DMA Control Register Ch.1 Rx FIFO Control & Status Register Ch.1 Rx Segment Register Ch. 1 Rx Buffer Base Register Ch. 1 Rx R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Tx/Rx Interrupt & data transfer mode Extended Features Control Receive Parameter and Control Tx/Rx misc. parameters & mode Tx. parameter and control Sync character or SDLC address field or Match Character 0 Sync character or SDLC flag or Match Character 1 Transmit Data Buffer Master Interrupt control Misc. Tx/Rx control register Clock Mode Control Lower Byte of Baud rate time constant Upper Byte of Baud rate time constant Misc. Control bits External/Status interrupt control Match Character 2 (wr16) Match Character 3 (wr17) Tx/Rx buffer and external status Receive condition status/residue code Interrupt Pending Register SDLC byte count low register SDLC byte count high & FIFO status Receive Buffer Loop/clock status
Rx DMA Registers 100h 101h 102h 104h 106h 108h 10Ah 10Ch 10Eh 110h 111h 112h 114h Control Register Control & Status Register Points to 64K data segment Wrap Reload Value for A15 -A8, A7-A0 reloaded to zero by hardware Upper Bound (plus 1) on A15-A0 Current Address pointer A15-A0 Corresponds to A15-A0 Byte Count, generates interrupt if enabled and byte count exceeded. 10Ch = Byte 0 = older, 10Dh = Byte 1 = younger 10Eh = Byte 2 = older, 10Fh = Byte 3 = younger Control Register Control & Status Register Points to 64K data segment Wrap Reload Value for A15 -A8, A7-A0 reloaded to zero by hardware 00h 00h 00h 00h 0000h 0000h 0000h 00h 00h 00h 00h 00h 00h 00h 00h
1999 Mar 29
13
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
MMR Name Buffer Bound Register Ch.1 Rx Address Pointer Reg Ch.1 Rx Byte Count Register Ch.1 Rx Data FIFO Register Ch.1 Lo Rx Data FIFO Register Ch.1 Hi Rx DMA Control Register Ch.2 Rx FIFO Control & Status Register Ch.2 Rx Segment Register Ch. 2 Rx Buffer Base Register Ch. 2 Rx Buffer Bound Register Ch.2 Rx Address Pointer Reg Ch.2 Rx Byte Count Register Ch.2 Rx Data FIFO Register Ch.2 Lo Rx Data FIFO Register Ch.2 Hi Rx DMA Control Register Ch.3 Rx FIFO Control & Status Register Ch.3 Rx Segment Register Ch. 3 Rx Buffer Base Register Ch. 3 Rx Buffer Bound Register Ch.3 Rx Address Pointer Reg Ch.3 Rx Byte Count Register Ch.3 Rx Data FIFO Register Ch.3 Lo Rx Data FIFO Register Ch.3 Hi Rx
Read/Write or Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Size 16 16 16 16 16 8 8 8 8 16 16 16 16 16 8 8 8 8 16 16 16 16 16
Address Offset 116h 118h 11Ah 11Ch 11Eh 120h 121h 122h 124h 126h 128h 12Ah 12Ch 12Eh 130h 131h 132h 134h 136h 138h 13Ah 13Ch 13Eh
Description Upper Bound (plus 1) on A15-A0 Current Address pointer A15-A0 Corresponds to A15-A0 Byte Count, generates interrupt if enabled and byte count exceeded. 11Ch = Byte 0 = older, 11Dh = Byte 1 = younger 11Eh = Byte 2 = older, 11Fh = Byte 3 = younger Control Register Control & Status Register Points to 64K data segment Wrap Reload Value for A15 -A8, A7-A0 reloaded to zero by hardware Upper Bound (plus 1) on A15-A0 Current Address pointer A15-A0 Corresponds to A15-A0 Byte Count, generates interrupt if enabled and byte count exceeded. 12Ch = Byte 0 = older, 12Dh = Byte 1 = younger 12Eh = Byte 2 = older, 12Fh = Byte 3 = younger Control Register Control & Status Register Points to 64K data segment Wrap Reload Value for A15 -A8, A7-A0 reloaded to zero by hardware Upper Bound (plus 1) on A15-A0 Current Address pointer A15-A0 Corresponds to A15-A0 Byte Count, generates interrupt if enabled and byte count exceeded. 13Ch = Byte 0 = older, 13Dh = Byte 1 = younger 13Eh = Byte 2 = older, 13Fh = Byte 3 = younger Control Register Control & Status Register Points to 64K data segment Wrap Reload Value for A15 -A8, A7-A0 reloaded to zero by hardware Upper Bound (plus 1) on A15-A0 Current Address pointer A15-A0 Corresponds to A15-A0 Byte Count, generates interrupt if enabled and byte count exceeded. 14C = Byte0 = older 14D = Byte 1 = younger 14E = Byte2 = older 14F = Byte3 = younger Control Register Control & Status Register Points to 64K data segment
Reset Value 0000h 0000h 0000h 00h 00h 00h 00h 00h 00h 00h 00h 0000h 0000h 0000h 00h 00h 00h 00h 00h 00h 00h 00h 0000h 0000h 0000h 00h 00h 00h 00h 00h 00h 00h 00h 0000h 0000h 0000h 0000h 0000h 00h 00h 00h
Tx DMA Registers DMA Control Register Ch.0 Tx FIFO Control & Status Register Ch.0 Tx Segment Register Ch. 0 Tx Buffer Base Register Ch. 0 Tx Buffer Bound Register Ch.0 Tx Address Pointer Reg Ch.0 Tx Byte Count Register Ch.0 Tx Data FIFO Register Ch.0 Tx Data FIFO Register Ch.0 Tx DMA Control Register Ch.1 Tx FIFO Control & Status Register Ch.1 Tx Segment Register Ch.1 Tx R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 16 16 16 16 16 8 8 8 140h 141h 142h 144h 146h 148h 14Ah 14Ch 14Eh 150h 151h 152h
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
MMR Name Buffer Base Register Ch.1 Tx Buffer Bound Register Ch.1 Tx Address Pointer Reg Ch.1 Tx Byte Count Register Ch.1 Tx Data FIFO Register Ch.1 Lo Tx Data FIFO Register Ch.1 Hi Tx DMA Control Register Ch.2 Tx FIFO Control & Status Register Ch.2 Tx Segment Register Ch.2 Tx Buffer Base Register Ch.2 Tx Buffer Bound Register Ch.2 Tx Address Pointer Reg Ch.2 Tx Byte Count Register Ch.2 Tx Data FIFO Register Ch.2 Lo Tx Data FIFO Register Ch.2 Hi Tx DMA Control Register Ch.3 Tx FIFO Control & Status Register Ch.3 Tx Segment Register Ch. 3 Tx Buffer Base Register Ch. 3 Tx Buffer Bound Register Ch.3 Tx Address Pointer Reg Ch.3 Tx Byte Count Register Ch.3 Tx Data FIFO Register Ch.3Lo Tx Data FIFO Register Ch.3 Hi Tx
Read/Write or Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Size 8 16 16 16 16 16 8 8 8 8 16 16 16 16 16 8 8 8 8 16 16 16 16 16
Address Offset 154h 156h 158h 15Ah 15Ch 15Eh 160h 161h 162h 164h 166h 168h 16Ah 16Ch 16Eh 170h 171h 172h 174h 176h 178h 17Ah 17Ch 17Eh 180-1FEh
Description Wrap Reload Value for A15-A8, A7-A0 reloaded to zero by hardware Upper Bound (plus 1) on A15-A0 Current Address pointer A15-A0 Corresponds to A15-A0 Byte Count, generates interrupt if enabled and byte count exceeded. Byte0 & 1 Byte2 & 3 Control Register Control & Status Register Points to 64K data segment Wrap Reload Value for A15 -A8, A7-A0 reloaded to zero by hardware Upper Bound (plus 1) on A15-A0 Current Address pointer A15-A0 Corresponds to A15-A0 Byte Count, generates interrupt if enabled and byte count exceeded. Byte0 & 1 Byte2 & 3 Control Register Control & Status Register Points to 64K data segment Wrap Reload Value for A15 -A8 A7-A0 reloaded to zero by hardware Upper Bound (plus 1) on A15-A0 Current Address pointer A15-A0 Corresponds to A15-A0 Byte Count, generates interrupt if enabled and byte count exceeded. Byte0 & 1 Byte2 & 3 RESERVED for future DMA 0 value disables counter interrupt. Same as above, for Rx1 Same as above, for Rx2 Same as above, for Rx3 DMA Interrupt Flags V.54 2047 Unit A Control & Status V.54 2047 Unit A Configuration V.54 2047 Unit A Threshold Cntr Lo V.54 2047 Unit A Threshold Cntr Hi V.54 2047 Unit A Error Counter V.54 2047 Unit B Control & Status V.54 2047 Unit B Configuration V.54 2047 Unit B Threshold Cntr Lo V.54 2047 Unit B Threshold Cntr Hi V.54 2047 Unit B Error Counter
Reset Value 00h 0000h 0000h 0000h 0000h 0000h 00h 00h 00h 00h 0000h 0000h 0000h 0000h 0000h 00h 00h 00h 00h 0000h 0000h 0000h 0000h 0000h -- 00h 00h 00h 00h 0000h 00h -- -- -- -- 00h -- -- -- --
Miscellaneous DMA Registers Rx Character Time Out Register Ch.0 Rx Character Time Out Register Ch.1 Rx Character Time Out Register Ch.2 Rx Character Time Out Register Ch.3 Global DMA Interrupt Register VACS VACFG VATCL VATCH VAEC VBCS VBCFG VBTCL VBTCH VBEC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 16 8 8 8 8 8 8 8 8 8 8 200h 202h 204h 206h 210h 240h 241h 242h 243h 244h 248h 249h 24Ah 24Bh 24Ch
V.54/2047 Registers
1999 Mar 29
15
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
MMR Name
Read/Write or Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Size
Address Offset 260h 262h 263h 270h 272h 280h 281h 282h 284h 285h 286h 288h 289h 28Ah 28Ch 28Dh 28Eh 290h 291h 292h 294h 295h 296h 2BEh 2BFh 2C0h 2C2h 2D0h 2D2h SCP Configuration SCP Data Byte
Description
Reset Value 8xh xx 00h 00h .. 00h .. -- 00h.. -- 0xh xxh xxh 0xh xx xx 0xh xx xx 0xh xx xx 0xh xx xx 3Fh 00h 0000h 0000h 0000h 00h
SCP Interface Registers SCPCFG SCPD SCPCS BDAEE BDCS B0CFG B0AM B0TMG B1CFG B1AM B1TMG B2CFG B2AM B2TMG B3CFG B3AM B3TMG B4CFG B4AM B4TMG B5CFG B5AM B5TMG MBCL RFSH MSI Control Register DataMask Register Hi-Pri Soft Ints & Pin Mux Control Reg. XInt2 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 8
SCP Control & Status Autobaud Echo Enable Autobaud Control & Status MIF Bank 0 Config MIF Bank 0 Base Address MIF Bank 0 Timing Params MIF Bank 1 Config MIF Bank 1 Base Address MIF Bank 1 Timing Params MIF Bank 2 Config MIF Bank 2 Base Address MIF Bank 2 Timing Params MIF Bank 3 Config MIF Bank 3 Base Address MIF Bank 3 Timing Params MIF Bank 4 Config MIF Bank 4 Base Address MIF Bank 4 Timing Params MIF Bank 5 Config MIF Bank 5 Base Address MIF Bank 5 Timing Params MIF Memory Bank Configuration Lock Register MIF Refresh Control IDL Mode Control Register IDL Mask Register Control bits for Hi-Priority Soft Ints, and Pin Mux External Interrupt 2 Control
Autobaud Registers
Memory Interface (MIF) Registers
IDL Interface Registers
Miscellaneous Registers
1999 Mar 29
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
FUNCTIONAL DESCRIPTION
The XA-SCC functions are described in the following sections. Because all blocks are thoroughly documented in either the IC25 XA Data Handbook, or the XA-SCC User Manual, only brief descriptions are given in this datasheet, in conjunction with references to the appropriate document.
ResetOut
The P3.2_Timer0_ResetOut pin provides an external indication (if the ResetOut function is enabled in the RSRSRC register) via an active low output when an internal reset occurs (internal reset is Reset instruction or Watchdog time out.) If the ResetOut function is enabled, the ResetOut pin will be driven low when a Watchdog reset occurs or the Reset instruction is executed. This signal may be used to inform other devices in the system that the XA-SCC has been internally reset. The ResetIn signal does NOT get passed on to ResetOut. When activated, the duration of the ResetOut pulse is 256 system clocks. WARNING: At power on time, from the time that power coming up is valid, the P3.2_Timer0_ResetOut pin may be driven low for any period from zero nanoseconds up to 258 system clocks. This is true independently of whether ResetIn is active or not.
XA CPU
The CPU is a 30MHz implementation of the standard XA CPU core. See the XA Data Handbook (IC25) for details. The CPU core is identical to the G3 core. See caveat in next paragraph about the Bus Interface Unit.
Bus Interface Unit (BIU)
This is the internal Bus, not the bus at the pins. This internal bus connects the CPU to the MIF (Memory and DRAM Controller.) WARNING: Immediately after reset, always write BTRH = 51h, followed by BTRL = 40h, in that order. Once written, do not change the values in these registers. Follow these two writes with five NOPS. Never write to the BCR register, it comes out of reset initialized to 07h, which is the only value that will work.
Reset Source Register
The reset source identification register (RSTSRC) indicates the cause of the most recent XA reset. The cause may have been an externally applied reset signal, execution of the RESET instruction, or a Watchdog reset. Figure 2 shows the fields in the RSTSRC register. If the ResetOut function is tied back into the ResetIn pin, then all resets will be external resets, and will thus appear as external resets in the reset source register. RSTSRC[7] enables the ResetOut function; 1 = Enabled, 0 = Disabled. See XA-SCC User Manual for details; RSTSRC[7] differs in function from most other XA derivatives.
Timers 0 and 1
Timers 0 and 1 are the standard XA-G3 timer 0 and 1. Each has an associated I/O pin and interrupt. See the XA-G3 data sheet in the IC25 XA Data Handbook for details. Many XA derivatives include a standard XA Timer 2, and standard UARTs. These blocks have been removed in order to provide other functions on the XA-SCC. There is no Timer 2, and the UARTs have been replaced with full function SCCs.
Watchdog Timer
This timer is a standard XA-G3 Watchdog Timer. See the G3 datasheet in IC25. Also, if you intend to use the Watchdog Timer to assert the ResetOut pin, see ResetOut in the XA-SCC User Manual. The Watchdog Timer is enabled at reset, and must be periodically fed to prevent timeout. If the watchdog times out, it will generate an internal reset; and if ResetOut is enabled the internal reset will generate a ResetOut pulse (active low pulse on ResetOut pin.)
XA CPU BIU
INTERNAL CPU BUS
Reset
On the XA-SCC there are two pins associated with reset. The ResetIn pin provides an external reset into the XA-SCC. The port pin P3.2_Timer0_ResetOut output can be configured as ResetOut. Because ResetOut does not reflect ResetIn, the ResetOut pin can be tied directly back into the ResetIn pin without other PC board logic. This configuration will make all resets (internal or external) appear to the XA as external resets. See the XA-SCC User Manual for a full discussion of the reset functions.
EXTERNAL MEMORY and I/O BUS
MIF and DRAM CONTROLLER
DMA CHANNELS x8
SU01123
Figure 2. XA CPU Core BIU (Bus Interface Unit)
ResetIn
The ResetIn function is the standard XA-G3 ResetIn function. The ResetIn signal does NOT get passed on to ResetOut. See the XA-SCC User Manual for details on reset.
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
RSTRC
Reg Type and Address = SFR 463h Not Bit Addressable MSB ROEN Bit: 7 -- 6 Function ResetOut function enable bit - see XA-SCC User Manual for details Reserved for future use. Should not be set to 1 by user programs. Reserved for future use. Should not be set to 1 by user programs. Reserved for future use. Should not be set to 1 by user programs. Reserved for future use. Should not be set to 1 by user programs. -- 5 -- 4 -- 3 R_WD 2 R_CMD 1 LSB R_EXT 0
Reset Value = see below
Bit RSTSRC.7 RSTSRC.6 RSTSRC.5 RSTSRC.4 RSTSRC.3 RSTSRC.2 RSTSRC.1 RSTSRC.0
Symbol ROEN - - - - R_WD R_CMD R_EXT
Indicates that the last reset was caused by a watchdog timer overflow (see WARNING.) Indicates that the last reset was caused by execution of the RESET instruction (see WARNING.) Indicates that the last reset was caused by the external ResetIn input.
WARNING: If ResetOut function is tied back into ResetIn pin, RSTSRC will always show external reset ONLY, because external reset always takes precedence over internal reset.
SU01124
Figure 3. RSTSRC Reset Source Register
DRAM Controller and Memory/IO Bus Interface (MIF)
In the memory or system bus interface terminology, generic bus cycles are synonymous with SRAM bus cycles, because these cycles are designed to service SRAMs, Flash, EEPROM, peripheral chips, etc. Chip select output pins function as either CS or RAS depending on whether the memory bank has been programmed as generic or DRAM. The XA-SCC has a highly programmable memory bus interface with a complete onboard DRAM controller. Most DRAMs (up to 8MBytes per RAS pin), SRAMs, Flash, ROMs, and peripheral chips can be connected to this interface with zero glue chips. The bus interface provides 6 mappable chip select outputs, five of which can be programmed to function as RAS strobes to DRAM. CAS generation, proper address multiplexing for a wide range of DRAM sizes, and refresh are all generated onboard. The bus timing for each individual
memory bank or peripheral can be programmed to accommodate slow or fast devices. Each memory bank and it's associated RAS (chip select pin in DRAM mode) output, can be programmed to access up to an 8MByte mappable address space in either EDO or FPM DRAM modes (up to a total of 16MB of DRAM, or 32MB if 16MB of data space and 16MB code space is elected. WARNING: Future XA-SCC derivatives may not support separate code and data spaces.) Each memory bank and associated chip select programmed for "generic" (SRAM, Flash, ROM, peripheral chips, etc) is capable of supporting a 1Mbyte address space (six chip selects can thus support 6MB of SRAM and other generic devices.) The Memory Interface can be programmed to support both Intel style and 68000 bus style SRAMs and peripherals.
1999 Mar 29
18
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Bus Interface Pins
For this discussion, see Figure 4. XA-SCC
CS5, RAS5, (or P3.1, RTS1) CS4, RAS4, (or P3.0, RTClk1) CS3, RAS3 CS2, RAS2 CS1, RAS1 CS0
A19-A0 (IF DRAM CYCLE, A22-A0 ARE TIME-MULTIPLEXED FOR RAS/CAS)
MIF
(MEMORY CONTROLLER)
D15-D0
ClkOut
CASH, BHE CASL, BLE
OE WE
WAIT, SIZE16
SU01125
Figure 4. Memory Bus Interface Signal Pins
Chip Selects and RAS pins
There are six chip select pins (CS5-CS0) mapped to six sets of bank control registers. The following attributes are individually programmable for each bank and associated chip select (or RAS if DRAM): bank on/off, address range, external device access time,
detailed bus strobe sequence, DRAM cycle or generic bus cycle, DRAM size if DRAM, and bus width. Pin CS0 is always generic in order to service the boot device, thus CS0 cannot be connected to DRAM.
WARNING: On the external bus, ALL XA-SCC reads are 16 bit Reads. If the CPU instruction only specifies 8 bits, then the CPU uses the appropriate byte, and discards the extra byte. Thus "8 Bit Reads" appear to be identical on the bus. On an 8 bit bus, this will appear as two consecutive 8 bit reads even though the CPU instruction specified a byte read Some 8 bit I/O devices (especially FIFOs) cannot operate correctly with 2 bytes being Read for a 1 Byte Read. The most common (and least expensive) solution is to operate these 8 bit devices on a 16 bit bus, and access them in software on all odd byte (or all even byte) boundaries. An added benefit of this technique is that byte reads are faster than on an 8 bit bus, because only 1 word is fetched (a single read) instead of 2 consecutive bytes.
Clock Output
The CLKOUT pin allows easier external bus interfacing in some situations. This output reflects the XTALIn clock input to the XA (referred to internally as CClk or System Clock), but is delayed to match the external bus outputs and strobes. The default is for
CLKOUT to be output enabled at reset, but it may be turned off (tri-state disabled) by software via the MICFG MMR. WARNING: The capacitive loading on this output must not exceed 40pf.
1999 Mar 29
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
CS0 CS
OE
128K x 8 ROM XA-SCC
A16-A0
D7-D0
CS1
RAS CASL CASH OE WE A17-A9 D15-D0 D15-D0 A8-A0
256K x 16 DRAM (HM514260DI)
CS2
RAS CASL CASH
OE A17-A8 A19-A0
OE WE A9-A0 D15-D0
1M x 16 DRAM (MT4C1M16C3)
D15-D0 CS3 BLE BHE RAS CASL CASH
32K x 16 SRAM
WE WE A15-A1 D15-D0
NOTE: During DRAM cycles only, the appropriate CAS Address will be multiplexed onto pins A17-A7 after the assertion or RAS and prior to the assertion of BHE (CASH) and BLE (CASL). See AC timing diagrams and the XA-SCC User Manual for complete details.
SU01126
Figure 5. Typical System Bus Configuration
1999 Mar 29
20
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Table 3. Memory Interface Control Registers
Register Name MRBH "MMR Base Address" High Reg Type SFR 8 bits Description This SFR is used to relocate the MMRs. It contains address bits a23-a16 of the base address for the 4 KByte Memory Mapped Register space. See XA-SCC User Manual for using this SFR to relocate the MMRs. Contains address bits a15-a12 of the base address for the 4 KByte Memory Mapped Register space. Contains the CLKOUT Enable bit.
MRBL
"MMR Base Address" Low
SFR 8 bits MMR 8 bits MMR 8 bits MMR 8 bits MMR 8 bits
MICFG
MIF Configuration
MBCL
Memory Bank Configuration Lock Bank i Configuration
Contains the bits for locking and unlocking the BiCFG Registers.
Contains the size, type, bus width, and enable bits for Memory Bank i.
BiCFG
BiAM
Bank i Base Address/DRAM Address Multiplexer Control Bank i Timing
Contains the base address bits and DRAM address multiplex control bits for Memory Bank i.
BiTMG
MMR 8 bits MMR 8 bits
Contains the timing control bits for Memory Bank i.
RFSH
Refresh Timing
Contains the refresh time constant and DRAM Refresh Timer enable bit.
Eight Channel DMA Controller
The XA-SCC has eight DMA channels; one Rx DMA channel dedicated to each SCC Receive (Rx) channel, and one Tx DMA channel dedicated to each SCC Transmit (Tx) channel. All DMA channels are optimized to support memory efficient circular data buffers in external memory. All DMA channels can also support traditional linear data buffers.
Transmit DMA Channel Modes
The four Tx channels have four DMA modes specifically designed for various applications of the attached SCCs. These modes are summarized in the following table. Full details for all DMA functions can be found in the DMA chapter of the XA-SCC User Manual.
Table 4. Tx DMA Modes Summary
Mode Non-SDLC/HDLC Tx Chaining Byte Count Source Header in memory Maskable Interrupt On stop Description DMA channel picks up header from memory at end of transmission. If byte count in header is greater than zero, then DMA transmits the number of bytes specified in the byte count. If byte count equals 0, then a maskable interrupt is generated. This process repeats until byte count in data header is zero. See XA-SCC User manual for details. Same as above, except DMA header distinguishes between fragment of packet and full pack. See XA-SCC User manual for details. Processor loads byte count into DMA. DMA sends that number of bytes, generates maskable interrupt, and stops. DMA runs until commanded to stop by processor. Everytime byte counter rolls over, a new maskable interrupt is generated.
SDLC/HDLC Tx Chaining
Header in memory
End of packet (not end of fragment)
Stop on TC
Processor loads Byte Count Register (for each fragment)
Byte count completed (Tx DMA stops)
Periodic Interrupt
Processor loads Byte Count Register (only once)
Each time byte count completed (Tx DMA continues)
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Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Receive DMA Channel Modes
The Rx DMA channels have four DMA modes specifically designed for various applications of the attached SCCs. These modes are summarized in the following table. For full details on implementation and use, see the XA-SCC User Manual.
Table 5. Rx DMA Modes Summary
Mode SDLC/HDLC Rx Chaining Byte Count Source DMA stores byte count in header in memory with data packet. Maskable Interrupt At end of received packet Description When a complete or aborted SDLC/HDLC packet has been received, the packet byte count and status information are stored in memory with the packet. A maskable interrupt is generated. The DMA channel runs until commanded to stop by the processor. It generates a maskable interrupt once per n bytes, where n is the number written once into the byte count register by the processor, thus an interrupt is generated once every n received bytes. Processor specifies time out period between incoming characters. If no character is received within that time, interrupt is generated. There are four match registers, each incoming character is compared to all four registers. When a matched character is stored in memory by DMA, a maskable interrupt is generated.
Periodic Interrupt
Loaded by processor into DMA, used only to determine the number of bytes between interrupts. Processor can infer the byte count from the DMA address pointer. Byte Count can be calculated by software from the DMA address pointer. Byte Count can be calculated by software from the DMA address pointer.
When Byte Counter reaches zero and is reloaded by DMA hardware from the byte count register. If no character is received within a specified time out period, then interrupt. When matched character is stored in memory.
Asynchronous Character Time Out
Asynchronous Character Match
DATA FIFO 3 DATA FIFO 1
DATA FIFO 2 DATA FIFO 0
DMA CONTROL SEGMENT BUFFER BASE BUFFER BOUND ADDRESS POINTER BYTE COUNT FIFO CONTROL Rx CHANNEL
Rx TIME OUT
DATA FIFO 3 DATA FIFO 1
DATA FIFO 2 DATA FIFO 0
DMA CONTROL SEGMENT BUFFER BASE BUFFER BOUND ADDRESS POINTER BYTE COUNT FIFO CONTROL Tx CHANNEL
SU01127
Figure 6. Rx and Tx DMA Registers
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Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
DMA Registers
In addition to the 16-bit Global DMA Interrupt Register (which is shared by all eight DMA channels), each DMA channel has seven control registers and a four-byte Data FIFO. The four Rx DMA channels have one additional register, the Rx Character Time Out Register. All DMA registers can be read and written in Memory Mapped Register (MMR) space. These registers are summarized below.
- Automatic CRC generation and checking (can be disabled for "pass-thru.") - Automatic zero-bit insertion and stripping. - Automatic partial byte residue code generation. - 14-bit Packet byte count stored in memory with received packet by DMA.
* Global DMA Interrupt Register (not shown in figure): All DMA
interrupt flags are in this register .
* Synchronous character oriented protocol features:
- Automatic CRC generation and checking. - One (Monosync) or two (Bisync) sync characters option. - External Sync option.
* DMA Control Register: Contains the master mode select and
interrupt enable bits for the channel.
* Segment Register: Holds A23-A16 (the current segment) of the
24-bit data buffer address.
* Transparent mode for bit-streaming applications. * Data encoding/decoding options:
- FM0 (Biphase Space) - FM1 (Biphase Mark) - NRZ - NRZI
* Buffer Base Register: Holds a pointer (A15-A8) to the lowest byte
in the memory buffer.
* Buffer Bound Register: Points to the first out-of-bounds address
above a circular buffer.
* Address Pointer Register: Points to a single byte or word in the
data buffer in memory. The 24-bit DMA address is formed by concatenating the contents of the Segment Register [A23-A16] with the contents of the Address Pointer Register [A15-A0].
* Programmable Baud Rate Generator, and 7/8 Clock Prescaler
option.
* Byte Count Register: Holds the initial number of bytes to be
transferred. In Tx Chaining mode, this register is not used because the byte count is brought into the byte counter from buffer headers in memory.
* Auto Echo and Local Loopback modes. * Supports hardware V.54/2047 generation and checking. * IDL (2B + D) supported on three SCC channels. Supports both "8
bit" and "10 bit" IDL.
IDL Time Division Multiplexor
SCC0, SCC1, and SCC2 can be internally connected to the on-chip IDL Interface, a glueless industry standard interface to Layer One devices such as U-Chips or S/T chips. Thus connected, the three SCCs can efficiently support the ISDN B1, B2, and D channels, while the IDL Interface time-multiplexes and demultiplexes the outgoing and incoming serial data streams. If software enables the IDL interface, then SCC0 is connected to IDL. Optionally, the software can also connect SCC1 and SCC2 to the IDL interface. SCC3 cannot be connected to the IDL interface. See the IDL chapter in the XA-SCC User Manual. In Figure 7, SCC0 is connected to IDL because IDL has been enabled by software. Software, in this example has also connected SCC1 to IDL, and has bypassed IDL for SCC2. SCC3 cannot be connected to IDL. If there are pins not being used by any of the SCCs, software can assign alternate functions to those pins; see the pin steering logic in the "Pins" appendix of the XA-SCC User Manual. For complete documentation on the IDL interface, see the IDL chapter in the XA-SCC User Manual.
* FIFO Control & Status Register: Holds the queuing order and
full/empty status for the Data FIFO Registers.
* Data FIFO Registers: A four-byte data FIFO buffer internal to the
DMA channel.
* Rx Char Time Out Register (RxCTOR, Rx DMA channels only):
Holds the initial value for an 8-bit character timeout countdown timer which can generate an interrupt.
Quad Serial Communications Controllers with Autobaud
* Asynchronous features:
- Asynchronous transfers up to 921.6Kbps - Can monitor input stream for up to four match characters per receiver - 5, 6, 7, or 8 data bits per character. - 1, 1.5, or 2 Stop bits per character. - Even or Odd parity generate and check. - Parity, Rx Overrun, and Framing Error detection. - Break detection. - Supports hardware Autobaud detection and response up to 921.6Kbps.
SCP Serial Interface Controller
The SCP Interface provides a full duplex, industry standard synchronous serial communication bus, similar to SPI and Microwire. SCP can be used to transfer control and status information to other chips, and for accessing serial flash devices. See the IDL interface chapter in the XA-SCC User Manual.
* SDLC/HDLC features:
- Automatic Flag and Abort Character generation and recognition.
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Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
IDL
PIN FUNCTION MUX
IDL On SCC 0
IDL On IF IDL ON IDL PINS, ELSE SCC0 PINS
SCC 1 SCC1 PINS OR GPIO SCC 2 SCC2 PINS OR GPIO
SCC 3
SCC3 PINS OR GPIO
The Pin Function Mux is used to enable alternate functions on unused pins.
SU01128
Figure 7. IDL Connection Options
Dual v.54 and 2047 Generators/Checkers
One of the two hardware generator/checkers which support the V.54/2047 line testing standards can be attached to each SCC. During V.54/2047 line testing sequences, the V.54/2047 units can be programmed to generate an interrupt when certain error criteria have been detected on the transmissions lines. The CPU can determine the quality of the transmission line by reading the V.54/2047 units' status registers.
Autobaud Detectors
Each SCC has it's own Autobaud detector, capable of baud rate detection up to 921.6Kbaud. The detectors can be programmed to automatically echo the industry standard autobaud sequences. They can be programmed to update the necessary control registers in the SCCs, and turn on the receiver; which in turn will automatically initiate DMA into memory of received data. Thus, once the baud rate is determined, reception begins without intervention from the processor. When the baud rate is detected, a maskable interrupt is sent to the processor. See the Autobaud chapter in the XA-SCC User Manual for details.
The power down mode stops the oscillator in order to absolutely minimize power. The processor can be made to exit power down mode via a reset or one of the external interrupt inputs (INT0 or INT1). This will occur if the interrupt is enabled and its priority is higher than that defined by IM3 through IM0. In power down mode, the power supply voltage may be reduced to the RAM keep-alive voltage VRAM. This retains the RAM, register, and SFR contents at the point where power down mode was entered. WARNING: VDD must be raised to within the operating range before power down mode is exited.
INTERRUPTS
In the XA architecture, all exceptions, including Reset, are handled in the same general exception structure. The highest priority exception is of course Reset, and it is non-maskable. All exceptions are vectored through the Exception Vector Table in low memory. Coming out of Reset, these vectors must be stored in non-volatile memory based at location 000000. Later in the boot sequence, DRAM or SRAM can be mapped into this address space if desired. There is a feature in the XA-SCC Memory Controller called "Bank Swap" that supports replacing the ROM vector table and other low memory with RAM. See the XA-SCC User Manual for details. The XA-SCC has a standard XA CPU Interrupt Controller, implemented with 15 Maskable Event Interrupts. Event Interrupts are defined as maskable interrupts usually generated by hardware events. However, in the XA-SCC, 4 of the 15 Event Interrupts are generated by software writing directly to the interrupt flag bit. These 4 interrupts are referred to as High Priority Software Interrupts. See the IC25 XA Data Handbook for a full explanation of the exception structure, including event interrupts, of the XA CPU. Because the High Priority Software Interrupts are specific to the XA-SCC, they are explained in the XA-SCC User Manual.
I/O PORT OUTPUT CONFIGURATION
Port input/output configurations are the same as standard XA ports: open drain, quasi-bidirectional, push-pull, and off (off means tri-state Hi-Z, and allows the pin to be used as an input. WARNING: At power on time, from the time that power coming up is valid, the P3.2_Timer0_ResetOut pin may be driven low for any period from zero nanoseconds up to 258 system clocks. This is true independently of whether ResetIn is active or not.
POWER REDUCTION MODES
The XA-SCC supports Idle and Power Down modes of power reduction. The idle mode leaves most peripherals running in order to allow them to activate the processor when an interrupt is generated.
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Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
XA CORE INTERRUPT CONTROLLER
DMAH DMA INTERRUPTS DMAL
CTS0 CD0 CTS1 CD1_INT2 SCC0/ SCC1
INTERRUPT ENABLE/ DISABLE BITS
INT2
CTS2 CD2 CTS3 CD3 INT0 INT1 AUTOBAUD 3-0 OR v.54_2047 1-0 SCC2/ SCC3 MASTER ENABLE "EA"
INTERRUPT TO XA CPU
SCP INTERFACE
TIMER 0
TIMER 1
4 HIGH PRIORITY SOFTWARE INTS HSWR 3-0
SU01129
Figure 8. XA-SCC Interrupt Structure Overview
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Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Table 6. SCC0 Interrupts (Interrupt structure is the same except for bit locations for all 4 SCCs)
Individual Enable Bit MMR Hex Offset Potential SCC0 Interrupt Rx Character Available - Source Bit MMR Hex Offset RR0[0] WR1[4:3] SDLC EOF CRC/Framing Error Rx Overrun Parity Error Tx Buffer Empty Break/Abort Tx Underrun/EOM CTS SYNC/HUNT DCD Zero Count WR1[2] See WR1[1] Break/Abort IE WR15[7] Tx Underrun/EOM IE WR15[6] CTS IE WR15[5] SYNC/HUNT IE WR15[4] DCD IE WR15[3] Zero Count IE WR15[1] - - - RR1[7] RR1[6] RR1[5] RR1[4] RR0[2] RR0[7] RR0[6] RR0[5] RR0[4] RR0[3] RR0[1] Tx Interrupt Enable WR1[1] Even Channel Tx IP RR3[4] Group Enable Bit(s) MMR Hex Offset Group Flag Bit MMR Hex Offset Even Channel Rx IP RR3[5] Master Enable Bit MMR Hex Offset SCC0/1 Master Interrupt Enable WR9[3]
Master External/ Status Interru t Interrupt Enable WR1[0]
Even Channel External/Status IP RR3[3]
EXCEPTION/TRAPS PRECEDENCE
DESCRIPTION Reset (h/w, watchdog, s/w) Breakpoint Trace Stack Overflow Divide by 0 User RETI TRAP 0-15 (software) VECTOR ADDRESS 0000-0003 0004-0007 0008-000B 000C-000F 0010-0013 0014-0017 0040-007F ARBITRATION RANKING 0 (High) 1 1 1 1 1 1
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Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
EVENT INTERRUPTS
Description Event Interrupt Source High Priority Software Interrupt 3 High Priority Software Interrupt 2 High Priority Software Interrupt 1 High Priority Software Interrupt 0 SCP Port Flag Bit HSWR3 MMR HSWR2 MMR HSWR1 MMR HSWR0 MMR SPFG SCPCS[3] MMR Interrupt Vector Address 00BF-00BC 00BB-00B8 00B7-00B4 00B3-00B0 00AF-00AC Enable Bit (SFR) EHSWR3 EHSWR2 EHSWR1 EHSWR0 ESCP Priority Register Bit Field (SFR) PHSWR3 PHSWR2 PHSWR1 PHSWR0 PSCP Arb. Rank 17 16 15 14 13
Autobaud and V.54/2047 multiple OR from Autobauds 3-0 & V.54/2047 A and B SCC "SCC2/3" Interrupt SCC "SCC0/1" Interrupt DMA "DMAH" Interrupt DMA "DMAL" Interrupt External Interrupt 2 (INT2) Timer 1 External Interrupt 1 (INT1) Timer 0 External Interrupt 0 (INT0) multiple OR from SCC2 & SCC3 multiple OR from SCC0 & SCC1 multiple OR from DMA multiple OR from DMA IE2 MMR TF1 SFR IE1 SFR TF0 SFR IE0 SFR
00AB-00A8
EAuto
PAutoB
12
00A7-00A4 00A3-00A0 009B- 0098 0097-0094 0093-0090 008F-008C 008B-0088 0087-0084 0083-0080
ESC23 ESC01 EDMAH EDMAL EX2 ET1 EX1 ET0 EX0
PSC23 PSC01 PDMAH PDMAL PX2 PT1 PX1 PT0 PX0
11 10 8 7 6 5 4 3 2
SOFTWARE INTERRUPTS
DESCRIPTION Software Interrupt 1 Software Interrupt 2 Software Interrupt 3 Software Interrupt 4 Software Interrupt 5 Software Interrupt 6 Software Interrupt 7 FLAG BIT SWR1 SWR2 SWR3 SWR4 SWR5 SWR6 SWR7 VECTOR ADDRESS 0100-0103 0104-0107 0108-010B 010C-010F 0110-0113 0114-0117 0118-011B ENABLE BIT SWE1 SWE2 SWE3 SWE4 SWE5 SWE6 SWE7 INTERRUPT PRIORITY (fixed at 1) (fixed at 2) (fixed at 3) (fixed at 4) (fixed at 5) (fixed at 6) (fixed at 7)
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Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
ABSOLUTE MAXIMUM RATINGS
PARAMETER Operating temperature under bias Storage temperature range Voltage on any other pin to VSS Maximum IOL per I/O pin Power dissipation (based on package heat transfer, not device power consumption) RATING -55 to +125 -65 to +150 -0.5 to VDD+0.5V 15 1.5 UNIT C C v mA W
PRELIMINARY DC ELECTRICAL CHARACTERISTICS
VDD = 5.0V "10% or 3.3V "10% unless otherwise specified; Tamb = -40C to +85C for industrial, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS 5.0V, 30 MHz IDD Power supply current operating current, 3.3V, 30 MHz 5.0V, 30 MHz IID IPDI VRAM VIL VIH VIH1 VOL Power supply current, Idle mode current 3.3V, 30 MHz Power supply current, Power Down mode1 RAM keep-alive voltage Input low voltage Input high voltage, except Xtal1, RST Input high voltage to Xtal1, RST Output low voltage all ports8 For both 3.0 & 5.0V IOL = 3.2mA, VDD = 4.5V IOL = 1.0mA, VDD = 3.0V VOH1 Output high voltage, all ports IOH = -100A, VDD = 4.5V IOH = -30A, VDD = 3.0V VOH2 Output high voltage, all ports IOH = 3.2mA, VDD = 4.5V IOH = 1.0mA, VDD = 3.0V CIO IIL ILI ITL Input/Output pin capacitance Logical 0 input current, all Input leakage current, all ports7 VIN = 0.45V VIN = VIL or VIH At VDD = 5.5V At VDD = 3.6V 2.4 2.0 2.4 2.2 15 -50 10 -650 -250 5.0V, 3.0V 1.5 -0.5 2.2 0.7 VDD 0.5 0.4 0.22VDD 50 65 500 mA A V V V V V V V V V V pF A A A A LIMITS MIN TYP 75 63 62 MAX 120 80 100 UNIT mA mA mA
ports6
Logical 1 to 0 transition current, all ports5
NOTES: 1. VDD must be raised to within the operating range before power down mode is exited. 2. Ports in quasi-bidirectional mode with weak pullup . 3. Ports in PUSH-PULL mode, both pullup and pulldown assumed to be the same strength. 4. In all output modes. 5. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when VIN is approximately 2V. 6. Measured with port in high impedance mode. 7. Measured with port in quasi-bidirectional mode. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15mA (*NOTE: This is 85C specification for VDD = 5V.) Maximum IOL per port pin: Maximum IOL per 8-bit port: 26mA 71mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
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Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
PRELIMINARY AC ELECTRICAL CHARACTERISTICS (5.0V "10%)1
VDD = 5.0V "10%, Tamb = -40_C to +85_C (industrial) SYMBOL All Cycles FC tC tCHCX tCLCX tCLCH tCHCL tAVSL tCHAH tCHAV tCHSH tCHSL tCODH tCPWH tCPWL tRP 25 25 25 25 25 All All All All All 26 System Clock Frequency System Clock Period = 1/FC XTALIN High Time XTALIN Low Time XTALIN Rise Time XTALIN Fall Time Address Valid to Strobe low Address hold after CLKOUT rising edge9 Delay from CLKOUT rising edge to address valid Delay from CLKOUT rising edge to Strobe High9 Delay from CLKOUT rising edge to Strobe ClkOut Duty Cycle High (into 40pF max.) (See Warning Note 5 on page 31.) Low9 0 33.33 tC* 0.5 tC* 0.4 - - tC - 21 1 - 30 - - - 5 5 - - 25 21 19 tCHCX+3 - - - MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE LIMITS PARAMETER MIN MAX UNIT
1 1
tCHCX-7 tC - 12 tC - 10 (n * tC) -16 note 8
13, 14, 16, CAS Pulse Width High 20, 21, 22 13, 21 24 CAS Pulse Width Low RAS precharge time, thus minimum RAS high time8
All DRAM cycles
Generic Data Read Only tAHDR 9, 16 Address hold (A19-A1 only, not A0) after CS, BLE, BHE rise at end of Generic Data Read Cycle (not code fetch) tC -12 - ns
Data Read and Instruction Fetch Cycles tDIS 9, 10, Data In Valid setup to ClkOut rising edge 12-14, 16, 17, 20, 21 Data In Valid hold after ClkOut rising edge2 10, 12, 13, OE high to XA Data Bus Driver Enable 16, 20, 21 25 - ns
tDIH tOHDE Write Cycles tCHDV tDVSL tSHAH tSHDH Refresh tCLRL Wait Input tWS 24 21 11, 16
0 tC - 14
- -
ns ns
Clock High to Data Valid Data Valid prior to Strobe Low Minimum Address Hold Time after strobe goes inactive Data hold after strobes (CS and BHE/BLE) high CAS low to RAS low WAIT setup (stable high or low) to CLKOUT rising edge
- tC - 23
25 - - - - - -
ns ns ns ns ns ns ns
tC - 25
tC - 25 tC - 15 20 0
tWH 24 WAIT hold (stable high or low) after CLKOUT rising edge NOTE: 1. See notes after the 3.3V AC timing table.
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Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
AC ELECTRICAL CHARACTERISTICS (3.3V "10%)
VDD = 3.3V "10%, Tamb = -40_C to +85_C (industrial) SYMBOL All Cycles FC tC tCHCX tCLCX tCLCH tCHCL tAVSL tCHAH tCHAV tCHSH tCHSL tCODH tCPWH tCPWL tRP 25 25 25 25 25 25 All All All All All 26 System Clock (internally called CClk) Frequency System Clock Period = 1/FC XTALIN High Time XTALIN Low Time XTALIN Rise Time XTALIN Fall Time Address Valid to Strobe low Address hold after CLKOUT rising edge9 Delay from CLKOUT rising edge to address valid Delay from CLKOUT rising edge to Strobe High9 Delay from CLKOUT rising edge to Strobe Low9 ClkOut Duty Cycle High (into 40pF max.) (See Warning Note 5 on page 31.) 0 33.33 tC* 0.5 tC* 0.4 - - tC - 21 1 - 1 1 tCHCX-7 tC - 12 tC - 10 (n * tC) -16 note 8 30 - - - 5 5 - - 30 28 25 tCHCX+3 - - - MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE LIMITS PARAMETER MIN MAX UNIT
13, 14, 16, CAS Pulse Width High 20, 21, 22 13, 21 24 CAS Pulse Width Low RAS precharge time, thus minimum RAS high time8
All DRAM cycles
Generic Data Read Only tAHDR 9, 16 Address hold (A19-A1 only, not A0) after CS, BLE, BHE rise at end of Generic Data Read Cycle (not code fetch) tC -12 - ns
Data Read and Instruction Fetch Cycles tDIS 9, 10, Data In Valid setup to ClkOut rising edge 12-14, 16, 17, 20, 21 Data In Valid hold after ClkOut rising edge2 10, 12, 13, OE high to XA Data Bus Driver Enable 16, 20, 21 32 - ns
tDIH tOHDE Write Cycles tCHDV tDVSL tSHAH tSHDH Refresh tCLRL Wait Input tWS 24 21 11, 16
0 tC - 19
- -
ns ns
Clock High to Data Valid Data Valid prior to Strobe Low Minimum Address Hold Time after strobe goes inactive Data hold after strobes (CS and BHE/BLE) high CAS low to RAS low WAIT setup (stable high or low) prior to CLKOUT rising edge
- tC - 23 tC - 25 tC - 25 tC - 15 25
30 - - - - -
ns ns ns ns ns ns
tWH 24 WAIT hold (stable high or low) after CLKOUT rising edge 0 - ns NOTES: 1. On a 16 bit bus, if only one byte is being written, then only one of BLE_CASL or BHE_CASH will go active. On an 8 bit bus, BLE_CASL goes active for all (odd or even address) accesses. BHE_CASH will not go active during any accesses on an 8 bit bus. 2. The bus timing is designed to make meeting hold time very straightforward without glue logic. On all generic reads and fetches, in order to meet hold time, the slave device should hold data valid on the bus until the earliest of CS, BHE/BLE, OE, goes high (inactive), or until the address changes. On all FPM DRAM reads and fetches, hold data valid on the bus until the earliest of RAS, CAS, or OE goes high (inactive.) On all EDO DRAM reads and fetches, hold data valid on the bus until a new CAS is asserted, or until OE goes high (inactive.) 3. To avoid tri-state fights during read cycles and fetch cycles, do not drive data bus until OE goes active
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Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
4. To meet hold time, EDO DRAM drives data onto the bus until OE rises, or until a new falling edge of CAS. 5. WARNING: ClkOut is specified at 40pF max. More than 40pf on ClkOut may significantly degrade the ClkOut waveform. Load capacitance for all outputs (except ClkOut) = 80pF. 6. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-SCC User Manual for details. 7. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from 2 to 16 bytes long. On a 16 bit bus, A3-A1 are incremented for each new word of the burst. On an 8 bit bus, A3-A0 are incremented for each new byte of the burst code fetch. 8. tRP is specified as the minimum high time (thus inactive) on each of the 5 individual CS_RAS[5:1] pins when such pin is programmed in the memory controller to service DRAM. The number of CClks (system clocks) in tRP is programmable, and is represented by n in the tRP equation in the AC tables. Regardless of what value is programmed into the control register, n will never be less than 2 clocks. Thus at 30MHz system clock, the minimum value for RAS precharge is tRP = ((2 * tC) -16) = ((2 * 33.33) - 16) = 50.6ns. As the system clock frequency FC, is slowed down, tC (system clock period) of course becomes greater, and thus tRP becomes greater. 9. The MIN value for this parameter is guaranteed by design and is not tested in production to the specified limit. In those cases where a maximum value is specified in the table for this parameter, it is tested.
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
CLKOUT
A0 tCHAV A19-A1 tCHAH
tCHSL CS tAVSL
tAHDR
(DOES NOT INCLUDE A0)
tCHSH BHE/BLE
OE
NOTE 3 tDIS
tDIH (NOTE 2)
D15-D0
NOTE: On Generic Data Reads, A0 can terminate a full clock period before A19-A1, and therefore should not be used on some peripheral devices. Figure 9. Generic (SRAM, ROM, Flash, IO Devices, etc.) Read on 16 Bit Bus
SU01130
CLKOUT tCHAV A[19:0] ADDRESS tCHSL CS tAVSL tCHSH tCHAV ADDRESS + 2 tCHAV ADDRESS + 4
BHE/BLE
OE
NOTE 3 tDIS tDIH NOTE 2 tDIH NOTE 2
tOHDE tDIH (NOTE 2) DRIVEN BY XA
tDIS
tDIS
D[15:0]
DRIVEN BY XA
NOTE: The processor can prefetch from one to eight words. NOTE 2: To meet the required Data In Hold time, data should be held on the bus at least until the earliest of CS, BHE, BLE, OE goes high, or until the address changes, whichever comes first.
SU01131
Figure 10. Generic Memory (SRAM, ROM, Flash, etc.) Burst Code Fetch on 16 Bit Bus
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Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
CLKOUT tCHAV A tCHSL CS tAVSL tSHAH tCHSH
BHE/BLE
NOTE 1
WE tCHDV tSHDH
D
SU01132
Figure 11. Generic (SRAM, IO Devices, etc.) Write
CLKOUT tCHAH A tCHAV tAVSL tCHSL CAS (BHE/BLE) tAVSL tCHSH OE tDIS D VALID DATA tOHDE tDIH NOTE 2 RAS ADDRESS tCHSL tCHAV CAS ADDRESS
tCHSH
RAS (CS)
SU01133
Figure 12. DRAM Single Read Cycle
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Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
CLKOUT tCHAH A tCHAV RAS (CS) tAVSL tCHSL CAS (BHE/BLE) tAVSL tCPWH tCPWL RAS ADDRESS tCHSL tCHAV tCHAH CAS ADDRESS tCHAV tCHAH
CAS ADDRESS + 2
tCHSH
tCHSH
OE
NOTE 3 tOHDE tDIS NOTE 4 tDIS WORD (from CAS ADDR + 2) NOTE 4
D[15:0]
DRIVEN BY XA
DRIVEN BY SLAVE DEVICE
WORD (from CAS ADDR)
4 Byte Fetch (1 word = 2 bytes) is shown on 16 bit bus, burst can be 2 to 16 bytes (1 to 8 words.) Note 4: To meet hold time, EDO DRAM drives valid Data until OE rises, or until new falling edge of CAS. Figure 13. DRAM EDO Burst Code Fetch on 16 Bit Bus
SU01134
CLKOUT tCHAV A tCHSL RAS tAVSL tCHSH CASL/CASH tCHSL OE tDIS D[15:0] INSTRUCTION NOTE 2 tDIS NOTE 2 tAVSL tCPWH tCHAV RAS ADDRESS tCHAH tCHSL CAS ADDRESS tCHAH tCHAV CAS ADDRESS + 2 tCHAH tCHSH tCHAV
INSTRUCTION
NOTE: The processor can prefetch from one to eight words (1 word = 2 bytes)
SU01135
Figure 14. DRAM FPM (Fast Page Mode) Burst Code Fetch
1999 Mar 29
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
CLKOUT tCHAV A tCHAH RAS ADDRESS tCHSL CAS ADDRESS tCHAH
tCHSL RAS (CS) tAVSL
tCHSH
CAS (BHE/BLE)
tAVSL
NOTE 1 tCHSH
WE tCHDV D VALID DATA
NOTE: If only one byte is being written, then only the corresponding CAS signal goes active. On 8 bit bus, CASH is inactive, and CASL goes active for both even and odd addressed bytes. : OE is inactive during all writes.
SU01136
Figure 15. DRAM Write (on 16 Bit Bus, also 8 Bit Write on 8 Bit Bus)
CLKOUT tCHAV A19-A1 A0 tCHSL CS tAVSL tCHAV tAHDR tCHSH EVEN BYTE ADDRESS ODD BYTE ADDRESS
BLE OE NOTE 3 tDIS D7-D0 NOTE 2 tDIS tDIH NOTE 2 DRIVEN BY XA tOHDE
On all cycles on 8 bit bus, BHE remains high (inactive). WARNING: On the external bus, ALL XA-SCC reads are 16 bit Reads. If the CPU instruction only specifies 8 bits, then the CPU uses the appropriate byte, and discards the extra byte. Thus "8 Bit Reads" and "16 bit Reads" appear to be identical on the bus. On an 8 bit bus, this will appear as two consecutive 8 bit reads even though the CPU will only use one of the two bytes. WARNING: Some 8 bit I/O devices (especially FIFOs) cannot operate correctly with 2 bytes being Read for a 1 Byte Read. The most common (and least expensive) solution is to operate these 8 bit devices on a 16 bit bus, and access them in software on all odd byte (or all even byte) boundaries. An added benefit of this technique is that byte reads are faster than on an 8 bit bus, because only 1 word is fetched (a single read) instead of 2 consecutive bytes.
1999 Mar 29
EEEEE EEEEE
DRIVEN BY XA
SU01137
Figure 16. Generic (SRAM, Flash, I/O Device, etc.) Read (16 Bit or 8 Bit) on 8 Bit Bus
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
ClkOut tCHAV EVEN ADDRESS tCHAV NOTE 3 tDIS D[7:0] tDIH Note 2 tDIS MS BYTE tDIH Note 2 tDIS tDIH Note 2 tDIS tCHSH tDIH Note 2 tCHAV ADDRESS + 1 tCHAV ADDRESS + 2 tCHAV ADDRESS + 3
OE, BLE, CS
LS BYTE
LS BYTE
MS BYTE
NOTES: BHE remains high (inactive) for all accesses on an 8 bit bus. A burst code fetch can be from 1 to 8 words (1 word = 2 bytes), a 2 word fetch is shown here. To meet the required Data In Hold time, data should be held on the bus at least until the earliest of CS, BLE, OE goes high, or until the address changes, whichever occurs first.
SU01138
Figure 17. Burst Code Fetch on 8 bit bus, Generic Memory
ClkOut tCHAV A19-A1 tCHSL tCHSH
A0 tCHSL CS tAVSL
tSHAH
tSHAH
tAVSL BLE, WE tSHDH D7-D0 tDVSL
OE is inactive during all writes.
SU01139
Figure 18. Generic 16 Bit Write on 8 Bit Bus
1999 Mar 29
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
CLKOUT tCHAV A tCHAV RAS ADDRESS tCHAH tCHSL RAS tAVSL tCHSH CASL (CASH STAYS HIGH) tCHSL OE tDIS D[7:0] LS BYTE tDIH (NOTE 2) tDIS MS BYTE NOTE 2 tAVSL tCPWH tCHSL tCHAV CAS ADDRESS EVEN tCHAH CAS ADDRESS ODD tCHAH tCHSH tCHAV
SU01140
Figure 19. 16 Bit Read on 8 Bit Bus, DRAM (both FPM and EDO)
1 ClkOut tCHAV A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
tCHAH RAS ADDR tCHSL CAS ADDR (EVEN) CAS ADDR (ODD) CAS ADDR (EVEN) CAS ADDR (ODD) tCHSH
RAS
tAVSL tCHSL tCHSH tCPWH
CASL
tAVSL
OE tDIS D7-D0 LS BYTE tDIH (NOTE 2) MS BYTE LS BYTE
tCHSH tOHDE tDIH (NOTE 2) MS BYTE
4 Byte Fetch is shown on 8 bit bus, burst can be 2 to 16 bytes. Data bus is sampled on the rising edge of clock 6, and every three clocks thereafter (clocks 6, 9, 12, and 15 in this example). NOTE 2: If data is held valid on the bus until the earliest of CAS, RAS, or OE rises, then the hold time is met.
SU01141
Figure 20. DRAM FPM (Fast Page Mode) Burst Code Fetch on 8 Bit Bus
1999 Mar 29
37
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
1 ClkOut tCHAV A
2
3
4
5
6
7
8
9
10
11
12
tCHAH RAS ADDRESS tCHSL CAS ADDR (EVEN) tCHSH CAS ADDR (ODD) CAS ADDR (EVEN) CAS ADDR (ODD) tCHSH
RAS
tAVSL tCHSL tCPWL
CASL
tAVSL
tCPWH
OE
NOTE 3 tDIS NOTE 4 MS BYTE LS BYTE
tCHSH tOHDE NOTE 4 MS BYTE
D7-D0
DRIVEN BY XA
DRIVEN BY SLAVE
LS BYTE
4 Byte Fetch is shown on 8 bit bus, burst can be 2 to 16 bytes. NOTE 4: To meet hold time, EDO DRAM drives Data until OE rises, or until a new falling edge of CAS. Data Bus is sampled on rising edge of clock 6, and every 2 clocks thereafter (clocks 6, 8, 10, and 12 in this example).
SU01142
Figure 21. EDO DRAM Burst Code Fetch on 8 Bit Bus
CLKOUT tCHAV A tCHAV RAS ADDRESS tCHAH tCHSL RAS (CS) tAVSL tCHSH CASL tAVSL tCPWH tCHSL CAS ADDRESS (EVEN) tCHAH tCHAV CAS ADDRESS (ODD) tCHAH tCHSH tCHAV
tCHSL WE tDVSL D[7:0] LS BYTE
tDVSL MS BYTE
SU01143
Figure 22. DRAM 16 Bit Write on 8 Bit Bus (FPM or EDO DRAMs)
1999 Mar 29
38
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
CLKOUT
tCHSL RAS tCLRL tCHSH
CASH, CASL
RAS and CAS terminate together. The active low portion of RAS can be programmed to last from 3 to 6 clock cycles. The high portion of RAS after Refresh can be programmed to last from 2 to 4 clock cycles. See Chapter 3 of XA-SCC User Manual.
SU01144
Figure 23. REFRESH
tRP
RAS
NOTE: tRP min. is specified for each of the 5 individual RAS pins (CS_RAS[5:1]). It is the minimum high time (thus RAS inactive) between two DRAM bus cycles on the same RAS pin.
SU01145
Figure 24. RAS Precharge Time
VDD - 0.5 0.7 VDD XTALIN 0.45 V 0.2 VDD - 0.1 tCHCX tCHCL tCLCX tC tCLCH
SU01146
Figure 25. External Clock Input Drive
tCODH
ClkOut
WARNING: ClkOut is specified into 40 pF max, do not overload.
SU01147
Figure 26. ClkOut Duty Cycle
1999 Mar 29
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Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
ClkOut
tWS
tWH
WAIT
tWS - Setup time of WAIT to riasing edge of ClkOut. tWH - Hold time of WAIT after ClkOut High.
SU01148
Figure 27. External WAIT Pin Timing
1999 Mar 29
40
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
mold mark
mold mark
1999 Mar 29
41
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 03-99 Document order number: 9397 750 05491
Philips Semiconductors
1999 Mar 29 42

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